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  • OcHungry - Thursday, April 19, 2007 - link

    AMD's 65nm K10 will beat Intel's 45nm Penryn by 20%, my prediction.
  • TA152H - Thursday, April 19, 2007 - link

    You picking the Cubs to win the World Series?
  • Thatguy97 - Thursday, June 18, 2015 - link

    lol funny after 8 years
  • Kougar - Thursday, April 19, 2007 - link

    Is there any info whatsoever regarding QuadCore pricing for the desktop with Kentsfield's successor? It would be very helpful to know if there might be a version of Yorkfield matching the $266 Q6600 price tag come next January... :)
  • theprodigalrebel - Wednesday, April 18, 2007 - link

    The Yorkfield-Kentsfield comparison looks correct.
    In the CPU-only Test, Yorkfield scores 887 points more (4957 vs 4070)
    In the Overall Test, Yorkfield scores 840 points more (11963 vs 11123)

    But the Yorkfield-Wolfdare scores look off...
    In the CPU-only Test, Yorkfield scores 1896 points more than Wolfdale. (4957 vs 3061)
    In the Overall Test, Yorkfield only scores 948 points more than Wolfdale. (11964 vs 11015)

    I'm guessing the Wolfdale Overall Score should read 10015?
  • Shintai - Thursday, April 19, 2007 - link

    Because 3Dmark score aint calculated like that.

    Check this.

    http://www.thg.ru/graphic/3dmark06/images/3dmarkca...">http://www.thg.ru/graphic/3dmark06/images/3dmarkca...

    And to add alittle fun:
    http://img374.imageshack.us/img374/5569/654545fd7....">http://img374.imageshack.us/img374/5569/654545fd7....

    If you take a E6600 CPU, and pair it with an inifity super performing GPU. Your score couldnt be over 35000.

    Same reason, just the other way. On why the score doesnt increase with the same value.
  • kilkennycat - Wednesday, April 18, 2007 - link

    I agree totally with the last sentence of this article. A Barcelona series of Penryn-like demonstrations and tests is many months overdue. Has AMD got serious design problems, or does the "emperor really have no clothes" with respect to Barcelona's performance ?

    Any hope of AMD recovering development costs with premium prices on the Barcelona family will be quashed if Intel chooses to counter with early release of Penryn-family CPUs and simultaneously undercut the AMD prices. Time to consider selling AMD stock short again?
  • archcommus - Wednesday, April 18, 2007 - link

    I fear that AMD has not released early benches because the performance is not what they're hoping for compared to what Intel is giving out. Intel is being boastful and giving out lots of info because they know what they have is good. If AMD had a really strong competitor they'd be doing the same, unless they're really trying to surprise Intel here, which of course would be great.

    I have no doubt Barcelona will be released on schedule, and I'm sure it'll outperform all Conroe setups, however I feel fairly certain that Penryn will outdo it and probably only a few months after.

    Sigh...
  • redbone75 - Wednesday, April 18, 2007 - link

    That's what I'm thinking as well. Remember back when AMD was about to release the Athlon 64 they would make all kinds of cocky comments about Intel's chips, even after purposefully delaying it a few times even though they could have released it earlier? It's because they knew what they had was going to kick some serious butt. It's not the same AMD now, and that should be cause for concern AMD supporters, unless what we're seeing is a new Intel that is now open about everything and a new AMD that is like the old Intel.
  • TA152H - Wednesday, April 18, 2007 - link

    Actually, AMD did toss out some numbers for people a few weeks ago, although they seemed inflated.

    It could be that the processor is clocking fairly low right now, with the 65nm manufacturing much newer to them than for Intel. Keep in mind, AMD's fastest parts for the Athlon 64, are 90nm still for now, so that indicates they don't have a great handle on 65nm right now, and of course the next processor is only being made on that. It might be more an indication of their manufacturing ability, or lack thereof, than an indictment against the processor.

    That's really the crux of the problem for AMD. The P8 isn't a terribly advanced processor, much less so than the technological marvel P7, but it works much better. AMD wouldn't have terribly difficult time matching the technology in it, and probably will. But, they are always trailing in manufacturing technology and there isn't an easy way to match it. It's a big advantage for Intel too, and one that doesn't seem to be going away.

    It might be, and probably will be, the Intel processors are superior for the desktop, and AMD for the servers where you have multiple sockets. It could easily come down to the design decision with regards to the location of the memory controller and the use of an FSB instead of point to point. AMD pays the price for it with one socket, Intel with multiple. Is there any mystery why AMD was showing off their server products and benchmarks, and not so forthcoming with desktop parts?

    Either way, Intel is going down the same road with Nehalem although on 32nm the tradeoffs might be a lot for single socket computers.
  • DigitalFreak - Wednesday, April 18, 2007 - link

    What, no comments Goty?
  • Goty - Wednesday, April 18, 2007 - link

    Nope, I agree with him. I'm not a blind fanboy like many would like to think. I'm actually quite rational in my arguments.
  • AdamK47 - Wednesday, April 18, 2007 - link

    32MB of L1 cache... nice.
  • Souka - Wednesday, April 18, 2007 - link

    yeah....need to replace KB with B on the L1 cache value...still makes the number look big, but uses small unit.

    Or how about just posing cache size in the industry standard KB units
  • coldpower27 - Wednesday, April 18, 2007 - link

    Probably borked no CPU-Z part.
  • vailr - Wednesday, April 18, 2007 - link

    Re: "Chipset Driver 8.1.1.1010"
    There's a beta Intel Inf driver Version 8.4.0.1010:
    http://www.station-drivers.com/page/intel%20chipse...">http://www.station-drivers.com/page/intel%20chipse...
    Also a newer CPU-Z version 1.39:
    http://www.cpuid.com/cpuz.php">http://www.cpuid.com/cpuz.php
    Actually, there's a CPU-Z version 1.39.2 out, but it's not posted on their web site.

  • KeypoX - Wednesday, April 18, 2007 - link

    "Or how about just posing cache size in the industry standard KB units"


    I think you mean kB kilobyte? Or did you mean kelvin byte KB?
  • Goty - Wednesday, April 18, 2007 - link

    People are posting how amazing this looks when in all actuality, it's pretty much nthing more than a speed bump. Looking at the results, Anand is guessing at a 10% performance increase when not considering the clockspeed. I can account for the other 9% right now: higher FSB, more cache. Penryn is just an evolutionary step, not revolutionary like the first Conroe CPUs and not really all that exciting IMHO.
  • erwos - Wednesday, April 18, 2007 - link

    If they can get the price down to $300-$400 for the quad-core variants, that'll be advancement enough. I desperately need to move our DVDs to H.264 or VC-1 to save space, but there's no way I'm paying $1000 for a quad-core CPU to do the task.

    At this point, I'm honestly desperate enough to grab the cheapie quad-core Xeons and overclock them, expensive motherboard or not.
  • coldpower27 - Wednesday, April 18, 2007 - link

    Wait for the old Kentsfield to have it's Q3 price drop to $266.
  • ShapeGSX - Wednesday, April 18, 2007 - link

    "I can account for the other 9% right now: higher FSB, more cache."

    Yes, and those are architectural changes to the chip.

    Look at the first page of the article. There aren't that many changes to these new chips. It is just an evolutionary step. Nobody is billing it as anything but. But an average 20% increase in just one year is still very impressive.

    Factor in the SSE4 boost that Divx encoding gets, and the leap is even more impressive.
  • KeypoX - Wednesday, April 18, 2007 - link

    while it is impressive to have a 20% increase it still beats the fact that it is mostly more clock speed and more cache. It will be more impressive to see if these can overclock like the c2d's ya know like 1-1.5ghz oc's on average. Then i will be impressed. Still waiting for the amd response too :(
  • defter - Wednesday, April 18, 2007 - link

    The clock speed difference is only about 9%, considering the scaling is not linear, clock speed alone accounts for maybe 6-7% performance increase. This means IPC is improved by over 10%, this is very impressive and reminds me of Willamette->Northwood transition. Compare this for example with AMD's 130nm->90nm and 90nm->65nm transitions that gave no increase in IPC at all.

    I many of you put too much emphasis on cache, in games, doubling the cache from 2MB to 4MB at 3GHz gives about 10-15% increase in performance: http://www.pconline.com.cn/diy/cpu/reviews/0704/99...">http://www.pconline.com.cn/diy/cpu/reviews/0704/99...

    Increasing the cache further by 50% to 6MB will naturally produce less benefits, thus the cache alone doesn't explain the >10% IPC improvement. There are also noticable improvements elsewhere.
  • Goty - Wednesday, April 18, 2007 - link

    Wow, you have no idea what you're talking about. IPC did not change at all with Penryn.
  • TA152H - Wednesday, April 18, 2007 - link

    Actually, you don't if you think that's true. Do you know what IPC means? Instructions Per Cycle? Based on the results published, there is no other explanation. Keeping in mind that there are always, or almost always, other factors involved in benchmarks besides raw CPU power, even getting an improvement equal to the clock speed increase is an accomplishment, when you exceed this you are obviously doing more per clock cycle. What other explanation is there?

    To emphasize this even further, just adding instructions that are used and do more work would increase the amount of work per cycle, although not technically not IPC. But, by the accepted meaning of the word, it would. Adding cache could also improve IPC, although if it comes with additionally latency it could hurt it too.

    So, he's right, it's only a matter of the extent of the improvement. I don't like blanket numbers like 10% because it acts like all applications behave the same, but certainly for the applications they ran, it did show an IPC improvement.
  • Goty - Wednesday, April 18, 2007 - link

    Exactly, IPC is Instructions Per Clock. Adding instructions like SSE4 won't increase the IPC (especially since there are no applications that I know of out there that utilize SSE4).

    I know that the only way to increase performance other than increasing the number of clock cycles you get in in a certain time frame is to increase the real IPC, I was referring to the maximum attainable by the architecture in a best case scenario (which is, I believe, also what the poster above me was referring to and what manufacturers mean when discussion IPC.).
  • TA152H - Wednesday, April 18, 2007 - link

    Your logic is flawed. Either SSE4 increases IPC or it doesn't, irrespective of what uses it currently. If you want to go by the actual name, it wouldn't regardless. If you go by the true, and useful, meaning of the word, work per cycle, they could in certain applications add to it.

    IPC does not mean best case scenario, it means in real world situations. The problem is, defining that. Rather than argue about it, just think about how useful a number would be that doesn't approach real world situations and just is based on how wide the processor is. It isn't useful at all, whereas something that got close to real world use would be a lot more useful. That's why it has that meaning. Maximum IPC isn't really that important, since it's more theoretical than real. Only how it relates to running software matters, but, of course, that's not easy to quantify because software is different from one app to another.

    IPC is a pretty useless number anyway, taken out of the context of clock speed. Just as useless as clock speed is taken outside of the context of IPC. Although, having said that, with x86, I think you're beginning to approach a level of maturity with the design (with the demise of the miserable P7) that IPC is pretty similar. Back in the bad old days, outside of the crappy 186 and 386, you'd see massive improvements. 286 was at least 2x faster than the 8086, probably closer to 3x. 486 was 2x faster than the 386, Pentium was at least 60% faster than the 486, and the Pentium Pro was roughly 35% faster and ran at higher clock speeds than the Pentium. Now, unless you really screw up with a design like the P7, you don't see these huge improvements. Put another way, the Athlon 64 isn't that much faster on an IPC basis than the magnificent K5 :P. For that matter, the Core 2 isn't a huge improvement over the Pentium Pro per cycle. Considering it's been 10 and 11 years respectively, IPC isn't growing nearly as fast as clock cycles, which are now also dead in the water. K5 ran at 116.7 in it's finest incarnation, PPro at 200. Roughly a 2500%, and 1500%. IPC is up maybe 25% in the same interval?
  • defter - Wednesday, April 18, 2007 - link

    quote:

    Put another way, the Athlon 64 isn't that much faster on an IPC basis than the magnificent K5 :P. For that matter, the Core 2 isn't a huge improvement over the Pentium Pro per cycle. Considering it's been 10 and 11 years respectively, IPC isn't growing nearly as fast as clock cycles, which are now also dead in the water. K5 ran at 116.7 in it's finest incarnation, PPro at 200. Roughly a 2500%, and 1500%. IPC is up maybe 25% in the same interval?


    You don't have any clue...

    How many FP instructions for example K5 could start and finish within let's say 10 cycles? Then compare those numbers to Athlon64....

    Then you could look at some Pentium III coppermine vs. Banias, Banias vs. Dothan, Dothan vs. Yonah single core and Yonah vs. Core2 benchmarks. You would see that there are huge real IPC increase between Pentium III and Core2. And Pentium III has significantly higher real IPC than original Pentium Pro.
  • TA152H - Wednesday, April 18, 2007 - link

    Actually, you don't have a clue. K5 wasn't known for floating point, and most people don't use floating point. I was talking about integer, that should have been obvious to you. The K5 had a horrible floating point unit, as did the K6.

    However, on integer, the K5 had extremely high IPC, but the clock rate was very low. The 116.7 K5 ran roughly the same speed as a Pentium 166. Did you know this before posting your stupid remarks?

    Pentium III has a big improvement over the Pentium Pro? Are you an idiot? They are essentially the same processor. On 16-bit code it would be faster, for sure, but who still runs that? The move from the Pentium Pro to the Pentium II was to address that, and make it less expensive because the Pentium Pro ran the L2 cache at full speed and was part of the processor package. It was too expensive for mainstream use. The Pentium III was a Pentium II with SSE, and the Coppermine added a 256K cache on the chip, instead of the 512K the Katmai had. So, it ended up where the Pentium Pro was, although the Coppermine's cache was faster. Was it a lot faster? No way, you obviously don't know what you're talking about.

    The Core 2 isn't that much faster than a Tualatin clock normalized either. As I said, they are slightly faster with each generation, but it's not enormous like the clock speeds. For two generations, it's really quite low. Look at the difference between the 286 and 486, or 386 and Pentium. You were seeing 3x to 4x the improvement. The difference in the Pentium Pro and Core 2 isn't even close to that, it's relatively minor. Compared to the clock speed, 200 MHz to 2.93 GHz. Hmmmm, you understand my point now?
  • defter - Thursday, April 19, 2007 - link

    quote:

    However, on integer, the K5 had extremely high IPC, but the clock rate was very low. The 116.7 K5 ran roughly the same speed as a Pentium 166. Did you know this before posting your stupid remarks?


    Of course I knew that. But being as fast as Pentium at 50% higher clock speed isn't that great accomplishment for modern CPUs like Athlon64. Most people don't use floating point??? Yeah, right, I wonder why AMD significantly improved FPU in Barcelona if nobody will use it....

    quote:

    Pentium III has a big improvement over the Pentium Pro? Are you an idiot? They are essentially the same processor. On 16-bit code it would be faster, for sure, but who still runs that? The move from the Pentium Pro to the Pentium II was to address that, and make it less expensive because the Pentium Pro ran the L2 cache at full speed and was part of the processor package. It was too expensive for mainstream use. The Pentium III was a Pentium II with SSE, and the Coppermine added a 256K cache on the chip, instead of the 512K the Katmai had. So, it ended up where the Pentium Pro was, although the Coppermine's cache was faster. Was it a lot faster? No way, you obviously don't know what you're talking about.


    LOL, I wonder who don't know what he is talking about. P3 Coppermine was about 10% faster than P3 Katmai at the same clock. When you then consider that original PPro had slow external L2 cache, and it lacked MMX and SSE instructions, you will notice that there is significant clock-to-clock performance improvement between PPro and Coppermine.

    quote:

    The Core 2 isn't that much faster than a Tualatin clock normalized either.


    Yes it is, Tualatin was clerly faster than Coppermine, Banias was clearly faster than Tualatin, Dothan was clearly faster than Banias, Yonah was clearly faster than Dothan (FP improvements) and Core2 was clearly faster than Yonah at the same clock speed. Thus there is a large difference between Core2 and P3 Coppermine.
  • TA152H - Thursday, April 19, 2007 - link

    OK, you clearly don't know what you're talking about.

    Pentium Pro didn't have an external cache, it was on the processor package itself, and ran at full CPU speed. The Pentium II was not faster than the Pentium Pro clock normalized, unless you ran 16-bit code or used MMX. The Pentium II and Katmai both were got progressively lower IPC as they got to higher clock speeds, except for the Katmai 600 MHz. The reason is simple, the cache wasn't any faster, except again in the 600 MHz version, and the memory ran at the same speed. So, each cycle you'd do worse. A Pentium Pro at 200 MHz had a higher IPC than a Katmai at 550 MHz, unless you were running instruction sets it didn't have. Also keep in mind there were Pentium Pros with 1 Meg cache (they sold for over 2k each!).

    The Tualatin was not significantly faster than the Coppermine, it was the same processor except for a prefetch in the L2 cache. The Pentium III-S came with 512K cache, and considering the horrible memory bandwidth these processors had at multipliers of 10.5, it helped. But again, that's a problem the Pentium Pro didn't have since it ran at 4x multiplier.

    The Pentium Pro, didn't even run 50% faster clock normalized than the Pentium. The Pentium Pro was the first processor Intel gave up on in terms of gaining huge IPC, and instead superpipelined it so they could get more clock cycles. Every prior generation ran at essentially the same speed on the same manufacturing process, and the main focus was on IPC. With the Pentium Pro it was a mixed focus, clock speed and some IPC. It wasn't 50% though, more like 30% IPC.

    Floating point has always been much easier to improve than integer, and with Intel upping the ante with Core 2, AMD was also compelled to. Up until the 486, they didn't even include a floating point processor on the chip, and they were expensive add ons. Even with the 486, they later created a 486SX that had a disabled floating point unit. For most people, floating point doesn't matter at all. VIA chips have particularly poor floating point still, a few years ago they were running it at half speed. Some people clearly use it, mostly game players but also other apps. But most don't. Everyone uses integer. Everyone.

    Your remarks about Yonah, et al, are off. Pentium M wasn't significantly faster than the Tualatin, nor was Yonah significantly faster than the Dothan. Actually, it was slower in some respects with the slow L2 cache. Again, I'm talking about integer, floating point is easy but it just doesn't matter as much. If you want floating point, why even bother with a crappy x86? Just get a Itanium and leave the dweebs with their x86 processors. I'm exaggerating, of course, some people need compatibility and decent floating point, but it's not not a huge space. Anyone doing serious floating point for engineering would be better off with a serious platform like the Itanium, and most people using computers don't use floating point. Unless you think alien blasters constitute 50% of the population. They don't. Most people grow up eventually and spend their time trying to capture Moscow :P.

  • defter - Wednesday, April 18, 2007 - link

    quote:

    Adding instructions like SSE4 won't increase the IPC


    No, but reducing latency of certain instructions (super shuffle, etc..) increases IPC.

    quote:

    I was referring to the maximum attainable by the architecture in a best case scenario (which is, I believe, also what the poster above me was referring to and what manufacturers mean when discussion IPC.).


    Usually when people talk about IPC they refer to the REAL IPC, who cares about theoretical numbers? And for example, cache makes an impact on real IPC. You will not be executing many instructions if you are waiting data to arrive from the main memory....
  • fitten - Wednesday, April 18, 2007 - link

    You can't hold IPC in a vacuum. Theoretically, every execution unit can execute in parallel. That's the maximum IPC that an architecture can have (modulo some things like retire rate, etc. but for simplicity that's good enough for an example) "Real" IPC comes from instruction streams from real programs. All sorts of things can interrupt IPC, good examples of this are branches and data hazards (instruction 2 depends on a result from instruction 1 to do its work so it obviously can't be executed completely in parallel).

    An instruction stream can have a maximum IPC as well and that is most often less than what the architecture it is running on is able to support. You can also recompile that program with better compilers that *may* (it is not guaranteed) extract more parallelism out of the instruction stream by deeper reordering of instructions, unrolling loops, etc. Some numbers thrown about are things like the average IPC of a typical x86 program is around 2.3. Certain applications may have higher average IPC.

    Penryn running an existing application faster than Core2Duo can be attributed to many things. Assuming IPC is the only way this could happen is probably not completely accurate (due to the IPC allowed by the program itself). Optimizing a few commonly used instruction execution pathways and dropping them by a single clock (out of 5 to 10 total for the instruction) could also show improvement.

    Anyway, without analysis of the applications, I guess we just have to take their word on what made it run faster.
  • DavenJ - Wednesday, April 18, 2007 - link

    In my original posting above, I stated that IPC should increase by 5-10% depending on the application if you normalize for cache, clock frequency and FSB. SSE4 and other minor architectural improvements are going into this die shrink. So we have a little more than just a move from 65 nm to 45 nm. The point of my original comments were to point out that the hype regarding Penryn is way over-rated. Intel is trying to make it seem like they have some great new killer product here that should be equated to the original Core 2 launch. I do admit that there is some great tech going into the 45 nm shrink regarding transistor materials and the like, but this chip is going to be pretty much the same product you get today at a faster speed bin.

    Overclock your Core 2 Extreme QX6800 to 3.33 GHz and 1333 MHz FSB (the awesome Core 2 architecture will easily allow this on air) and run some benchmarks. You won't be far off the mark from the Penryn results displayed here. Those applications that use the extra L2 cache will be slightly higher and the rest will be about the same (no SSE4 applications out yet).

    What Intel should be shouting at the rooftops and releasing the results to Anandtech and others is power draw of the chip. This chip is supposed to increase performance/watt way up but not a single data point was released towards this fact.

    Either yields are bad or the PR spin is daft.
  • defter - Wednesday, April 18, 2007 - link

    quote:

    I was referring to the maximum attainable by the architecture in a best case scenario (which is, I believe, also what the poster above me was referring to and what manufacturers mean when discussion IPC.).


    I don't that hype is overrated. 10% clock-to-clock improvement with higher clockspeed is nothing to sneeze at. When was the last time we got similar improvement in desktop space? Let's see
    130nm K8 -> 90nm K8: no clock-to-clock improvement and initially lower clockspeed
    90nm K8 -> 65nm K8: no clock-to-clock improvement and initially lower clockspeed
    Northwood -> Prescott: no clock-to-clock improvement and higher power consumption
    Prescott -> Presler: no clock-to-clock improvement

    We need to go as far as to Willamette->Northwood transition that happened over 5 years ago to see similar results from a die shrink.

    quote:

    What Intel should be shouting at the rooftops and releasing the results to Anandtech and others is power draw of the chip.


    They have released it already. Check the last Penryn article, dual core Penryn based CPUs will have 65W TDP and quad core CPUs will have 130W TDP. I don't see any reasons why those demo system would have exceeded those values. Now, how many Kentsfield CPUs can work at 3.33GHz while mantaining 130W TDP?

    quote:

    Either yields are bad


    Based on what facts are you making claims about yields???
  • Spoelie - Wednesday, April 18, 2007 - link

    I do remember venice being faster than newcastle clock for clock... And I'm not talking about taking advantage of the extra SSE3 instructions.
    Wasn't much, up to a max of 5% or so, but yes it was there :p
  • defter - Thursday, April 19, 2007 - link

    Venice wasn't AMD's first 90nm CPU, Winchester was. And there weren't any clock-to-clock improvement between Winchester and Newcastle.
  • TA152H - Wednesday, April 18, 2007 - link

    Not necessarily, it is much more probable that they are not on final silicon and the power use will drop when the release it. Actually, that's almost a certainty to be true, but speculation as to why.

    Put another way, why would you release numbers now when you know they will be much better when the product is introduced? You'd downgrade your processor for no apparent reason, and lose sales. Keep in mind purchasing decisions for big companies are planned and budgeted, and if you release bad numbers based on pre-release silicon, you are going to lose sales. Having spoken to Intel reps in the past, they are telling their customers, unofficially, what to expect from the chips in terms of power when it is released. They aren't telling them the current power use, of course, and they can't officially give the power use until they have chips that use it. That could be a disaster if things don't go exactly as planned.
  • coldpower27 - Wednesday, April 18, 2007 - link

    And those are performance enhancing features, what is impressive is that these features are brought to you at the same power envelopes that existing Conroe's have now.

    No one is expecting a completely architectural overhaul here this is the cost cutting generation, the fact that is more then that this time around, is awesome.
  • DavenJ - Wednesday, April 18, 2007 - link

    Why doesn't Anand overclock a quad-core QX6800 to 3.33 GHz and 1333 MHz FSB and compare the number then? That way, the chips are more identical except for cache.

    Take the new numbers, take off 5-10% of the performance because of the increased cache and then you would have a good clock for clock comparison to see what performance if any the new chip features have. I bet Penryn has negligible IPC increase over Core 2. This is a bunch of PR spin and nothing more.
  • GlassHouse69 - Wednesday, April 18, 2007 - link

    I would agree that things arent so fantastic with this chip except for cheaper production and lower power which is neato.

    however, the extra cache is useless for much although more cache always speeds things up.

    if the chip had a real on die mem controller then it wouldnt need half that cache.....

    pwnd
  • coldpower27 - Wednesday, April 18, 2007 - link

    Sigh, it's not Intel's problem that AMD has lousy cache technology Intel has great expertise in cache so they can throw alot of it on.

    IMC while is one way to do things isn't the only way to do things, in the meantime, this is a nice boost over an existing design.
  • TA152H - Wednesday, April 18, 2007 - link

    You apparently aren't taking into account that Intel has a bigger cache BECAUSE they don't waste real estate on the memory controller. Both companies can't make huge processors for the mainstream market, because they'd be too expensive so they have to choose what to spend size on. Have you seen an Athlon 64 die? The memory controller is a very large part of it. Memory is very small for the amount of transistors it uses, and you can get a lot of bang for the buck by adding cache in that space instead of a memory controller.

    One thing, it's almost funny how poorly informed people are about cache. A bigger cache does NOT make for better speed in every case. The larger the cache, the more time it takes to read, in general terms. Look at the 65 nm AMD processors; they added wait states so they could add a larger cache later on. And it's not a clear as saying that they know it's better if they add so much cache for so many wait states, it depends on the applications. Plus, you increase power use, and dissipate more heat, and sometimes the cache is the limiting factor in how fast you can clock a processor unless you add the wait states (Pentium III Coppermine, for example, had a miserable time getting over 1 GHz because of the L2 cache, the Celeron version with an additional wait state got to 1.1 GHz).

    I also think the level of expectation is out of control for these hobbyist site viewers. This is just a shrink, or should be, and any boost at all should be viewed favorably. The fact they did more than a shrink is great, and if they get even four percent I'd view that as excellent, it was only a year ago they introduced a fantastic processor. Comparing the changes from the P7 to the P8 is uninformed, not only because the P7 sucked bad, and was probably Intel's worst processor (or maybe the 432, or i860, or 8008?, etc...), but also because it was a complete overhaul vis-a-vis the P7, and even compared to a P6+ (Pentium M line), it had major changes.

    Comparing an AMD processor to this group would have been absurd. First of all, they were doing it under Intel's supervision, and also this is not a selling processor. You'd have to compare it to AMD's next generation, which they aren't giving out yet, so the best thing is to just compare it with Intel's current stuff so people can extrapolate from that how it will compare to AMD's existing processors, and upcoming processors.

    Anyone counting AMD out is an idiot, plain and simple. While we may not have specifics on the product, we do have the actions of both Intel and AMD to look at, and they all point to the product being excellent, and at least roughly as good as Intel's. Intel is revealing all sorts of stuff they wouldn't otherwise do, and AMD is desperately clinging to market share even at the cost of losing money, so when their new core comes out, they will be in all these lines of machines from companies. Intel is trying to break them before it happens. Why if the product sucks? It doesn't, Intel knows they have problems on the horizon and everything they've done has demonstrated that, there isn't really any other explanation. You don't do that when the upcoming competitor's product sucks, you give too much away for almost no benefit. And they do know what it can do, and they are doing what they can to limit the impact of it.
  • coldpower27 - Wednesday, April 18, 2007 - link

    Oh but I am that is only part of the equation, Intel does have better cache density on a given process then AMD does. Working with Itanium has made that a necessity.

    Yeah, a IMC does indeed take alot of die area, core logic is on the lower end of the transistor density on a given process.

    IMC + HSI doesn't help either in ALL cases that don't stress memory bandwidth so this argument is basically tit for tat. Larger caches help as you have more available memory closer to the processor, how much in each situation varies on how much data needs to be worked on. IMC does the same thing except instead of making the LV2 bigger, you make the latency between main memory and the CPU lower so you can get data quicker, which is the same idea as more LV2 more data on hand.

    Cache is typically the lowest power stuff on the CPU die, it the main core logic which increases power consumption for the most part.

    This is more then your usual optical shrink. Intel for the most part doesn't do those, they usually add more cache with each successive generation. There are some improvements to the core functionality, not an major overhaul like Yonah to Merom but enough to maybe give some nice boosts, no more then 10% at the most I would gather on an IPC level.

    Now your just going off on a wild tangent, the NetBurst architecture was designed to be sexy and flashy and worked well for quite sometime. It sold on CPU clockspeed as most people don't understand the concept of IPC, and it wasn't till sub 100nm that heat issue became the limiting factor.

    Well having the reference point there would be interesting, as we need to see how much AMD needs to improve to get to Merom/Conroe and later on Penryn/Wolfdale levels. We want to compare it to Bareclona but AMD's has been so tight lipped on that, so such a comparison can't be done.

    Of course AMD isn't finished, though I don't believe your confidence in AMD is as well founded as it may seem. AMD so far has only given us vague conclusions on Barcelona performance and pretty much showed a scenario heavily playing to AMD's own strengths specFP would run best on AMD as one it's quite memory bandwidth dependent so with Barcelona vs Clovertown, Intel's FSB starts to become a limiting factor. As well K8 is already pretty much at parity with regard to FP resources to Core, K10 is known to be doubling the FP resources so it doing well in FP is not surprising.

    Intel is a very smart corporation, and know how to generate awareness and interest in it's products unlike AMD. The information release such as this is a great PR move as it shows Intel is confident and doesn't have anything to hide, and doesn't leave the customer always guessing. It also hurts AMD as some people will be waiting for these new products to arrive since at least with these you know what's going to happen and they are a safe bet.

    You have to understand Intel is currently focused on regaining mindshare and marketshare. What Intel has done today is quite a marketing coup, it showed 45nm benchmarks before AMD has released any information on anything other then synthetics on their K10.

    There shouldn't be any doubt that K10 will be superior to K8, since the design is evolutionary, so it will be a good product, but the question we all want to know. Will it beat Intel's equivalents in the desktop environment? In Single Socket systems FSB is just fine and basically not much of an issue. I expect Bareclona to reamin ahead against Clovertown and Tigerton, but the lead will have substantially deminished in the 4P sector as the jump from Santa Rosa to Barcelona is smaller then Tulsa to Tigerton.
  • TA152H - Wednesday, April 18, 2007 - link

    IMC + HSI stuff is your own argument. Don't put words in my mouth, I never said it always did help. I was just saying that larger isn't always better with respect to caches, nothing more, nothing less.

    Caches do take power, why do they power some of them down in mobiles if they aren't significant?

    The P7 was never a good processor, it sucked from day one and sucked worse as time went along. It was a marketing tool, and a technological showpiece, but it sucked in terms of being useful. There were some benchmarks where it could beat the K7, for sure, but at what cost? The processor was enormous by comparison, used massive amounts of heat, and was being compared to an older processor. They had to kill off the Tualatin with enormous prices because it was too good vis-a-vis the P7, this despite a severe memory bottleneck on it. So, I don't buy it was ever good, I was horrified when I learned about it. The size, heat, etc... compared to performance was absolutely terrible from day one, and only their manufacturing capability allowed them to remain competitive, until the K8. The Prescott just made things worse, but it was all sizzle; that steak was made out of horse.

    Heat is always an issue. That's why you'd get higher clock speeds with better cooling even with the K7 and P6. However, the miserable P7 design was the first one that heat became a huge problem well before the speed the transistors could work at was reached. It's also always an issue because you have to cool it, not only with fans in the case, but also, for a server room, you have to get it out of the building. It's always an issue, and the P7 was the worst processor ever made, relatively speaking, in that regard. Just horrible.

    Of course this is more than a shrink. That much is beyond obvious.

    If you can't extrapolate the data from the comparison to see how much AMD needs to improve, I doubt putting them in there would help that much. Besides, for that to matter, you'd have to be able to adequately define how much AMD CAN improve. You can't, I can't, so it's meaningless. The Core 2 is a fine processor, but it's not particularly advanced. AMD should have no problem adding such things as memory disambiguation, and in fact have already stated they have. The end product won't trail Intel by much, if any, how could it? The main problem is the scheduling, which AMD says they have fixed in much the same way Intel did with Core 2. The difference was, the P6 was always better than the K7 and K8, although not as wide, so they'll end up the same place. There may be differences, but they aren't going to be enormous.

    Intel is a really stupid corporation too, look at the P7. They really understood the market right with RDRAM and Itanium, right? Sometimes they get it right, sometimes they don't, but talking about a company that has screwed up as much as they reverently is absurd. Were it not for their egregious mistakes, AMD wouldn't have won 25+ market share, would they?

    Releasing information too soon is more often than not a mistake. You have to have a reason for it, or you're plain stupid. They do, obviously, they want to distract attention from AMD. If AMD gets people too excited about a product they aren't shipping, guess what people do? They wait and don't buy stuff already out there. That's why companies typically don't say too much or build up too much excitement, people don't buy what they're selling now and we already know AMD is having problems selling processors. This would help them how? So, people on hobby site chatboards would say nicer things about them? I don't think they care that much; if the processor is great when they release it, they don't need to say too much beforehand. If it is great, they'd be foolish to since it would kill existing sales. For businesses, and such, they are probably saying more, but I don't have any contacts with AMD anymore so I don't know for sure. They are giving people server numbers, and that will make people wait before doing their budget. So, I think they're being extremely rational. Intel is saying an awful lot, and it makes me wonder why. I wouldn't even consider buying a Conroe now, I'll wait for the Penryn, or AMD's chip. I was on the fence before reading this, since my development machine is driving me crazy it's so slow (2.4 GHz AMD).

    Everything is evolutionary now, sort of. The P6 was the starting point for everything but the horrible P7. The Athlon wasn't that different. The Athlon 64 isn't that different from the Athlon. The Pentium M's weren't that different from the Tualatin, and the Yonah wasn't that different either. The Core is a little wider, and has better scheduling, but it's just an evolutionary step. The P7 was revolutionary, with the amazing array of technology it had, and so was the Itanium, but one is dead, and the other currently irrelevant except in the HPC market.




  • Zirconium - Wednesday, April 18, 2007 - link

    The Wolfdale processor has the same FSB as the X6800. It does, however, have 6 megs of cache. Does that entirely account for the other ~10%? Maybe, maybe not. In either case, if I had a choice between a Conroe and a Wolfdale at the same clock, I'd probably take the Wolfdale.
  • Komodo - Wednesday, April 18, 2007 - link

    The difference between 18 and 38 sec is not 52,6% but 111% (in DivX 6.6 Results).
  • retrospooty - Wednesday, April 18, 2007 - link

    Zat you santy clause? ;)
  • JarredWalton - Wednesday, April 18, 2007 - link

    Corrected, along with the HL2 percentage being off.
  • dm - Wednesday, April 18, 2007 - link

    The future looks bright with Penryn :)
  • Regs - Wednesday, April 18, 2007 - link

    Though all we've been getting is words with no definitions. AMD has to show something by the end of this month. I see no excuse otherwise. They can't continue to throw us bones to pick at. That time ended over 6 months ago.
  • JackPack - Wednesday, April 18, 2007 - link

    I'm sure AMD felt confident when they thought Barcelona was up against Xeon X5355 (2.66 GHz). Then, they realized they were up against 3.0 GHz. Now, it's Yorkfield at 3.33 GHz.
  • Souka - Wednesday, April 18, 2007 - link

    I'd like to see 2 current top gen AMD chips included in bench... just to show how much of a difference there is...



  • Roy2001 - Wednesday, April 18, 2007 - link

    I'd like to see 2 current top gen AMD chips included in bench... just to show how much of a difference there is...
    -------------------------------------------------------------------------
    Man, 6000+ falls short of E6700 and barely beats E6600 if not equal. So AMD has no player in Penryn arena, at least for now. If they cannot crank Barcelona frequency higher, then they have no chance. 2.3Ghz is simply far from enough to compete with 3.33Ghz Penryn.
  • Goty - Wednesday, April 18, 2007 - link

    You're assuming that Barcelona won't outperform Penryn on an IPC basis, which nobody can say yet.
  • ShapeGSX - Wednesday, April 18, 2007 - link

    That brings up a good point. Why is it that we haven't at least seen a demo of Barcelona like Intel has shown us for Conroe (last year) and Penryn?
  • Goty - Wednesday, April 18, 2007 - link

    AMD isn't in the habit of showing off it's technology very far in advance of its launch.
  • defter - Wednesday, April 18, 2007 - link

    Yeah right, they showed a running K8 system "only" more than a year before the launch...
  • Roy2001 - Wednesday, April 18, 2007 - link

    Clock to clock, Barcelona could be faster. I just mean 2.3Ghz is too slow to compete with Penryn. If AMD can make it faster, say 2.8Ghz, it could compete with Penryn. This is just my 2 cents.
  • Goty - Wednesday, April 18, 2007 - link

    If Barcelona came in at 2.3GHz with twice the IPC as Conroe/Penryn (this is hyperbole, I know it's not going to), it would wipe the floor with either processor. You can't speculate on the performance without knowing these kinds of details.
  • Roy2001 - Wednesday, April 18, 2007 - link

    Well, Barcelona vs. Penryn/Conroe is not like Athlon 64 vs. Pentium 4. AMD just need RAW speed with Barcelona. Otherwise they are rather in danger position than we expected. AMD does not have the man power and money to develop mArchitecture every 2 years. Intel's strategy is much like nVidia's now, one generation new structure and one generation die shrink.
  • GlassHouse69 - Wednesday, April 18, 2007 - link

    2 months ago, amd released information that the new technology will speed things up vs raw clock speed....


    raw clock speed is winning.... amd might be toast :(

    sux i hate intel
  • KhoiFather - Wednesday, April 18, 2007 - link

    Man, I just hope I can afford one of these bad boys when it comes out to the public. Its just amazing I tell ya and Intel just keeps rolling out their new CPUs. I'm guessing I'm going to need to upgrade my Gigabyte DS3 to another mobo to support the new Yorkfield CPU eh?
  • qquizz - Wednesday, April 18, 2007 - link

    These won't even be availabe til sometime in 2008, at least that is my understanding. So you got plenty of time to save up your money and by then I will talk you into buying AMD anyway In conclusion, I agree with the title of your post ;)
  • KCjoker - Wednesday, April 18, 2007 - link

    That's what I'd like to know, which current IF ANY mobo's will work with these new CPU's.
  • Webgod - Saturday, April 21, 2007 - link

    bump.

    If the Wolfdale is just a faster 45nm C2D, will the currently shipping Bad Axe 2's work with it with perhaps a new BIOS?? I mean Intel has a history of requiring all new gear. The Bad Axe 1 had to be tweaked to work with the Conroe C2D. Surely even if they're discontinuing the Bad Axe 2 (eventually sure) they could see that passing on the compatibility would get them off the shelves. And, it would be good PR for a change as far as compatibility goes, historically.

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